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ISL59424, ISL59445
Data Sheet September 8, 2005 FN7456.2
1GHz Triple Multiplexing Amplifiers
The ISL59424 and ISL59445 are 1GHz bandwidth multiplexing amplifiers designed primarily for video input switching. These MUX-amps exhibit a fixed gain of 1 and also feature a high speed three-state to enable the output of multiple devices to be wired together. All logic inputs have pull-downs to ground and may be left floating. The EN pin, when pulled high, sets the ISL59424 and ISL59445 in to low current mode - consuming just 15mW. An added feature in the ISL59424 is a latch enable function (LE) that allows independent logic control using a common logic bus. When LE is high the last logic state is preserved.
TABLE 1. CHANNEL SELECT LOGIC TABLE ISL59424 S0 0 1 X X X ENABLE 0 0 1 0 0 HIZ 0 0 X 1 0 LE 0 0 X X 1 OUTPUT INO (A, B, C) IN1 (A, B, C) Power Down High Z Last S0 State Preserved
Features
* Triple 2:1 and 4:1 Multiplexers for RGB * Internally Set Gain-of-1 * High Speed Three-state Outputs (HIZ) * Power-down Mode (EN) * Latch Enable (ISL59424) * 5V Operation * 1200 V/sec Slew Rate * 1GHz Bandwidth * Latched Select Pin (ISL59424) * Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
* HDTV/DTV Analog Inputs * Video Projectors * Computer Monitors * Set-top Boxes * Security Video
TABLE 2. CHANNEL SELECT LOGIC TABLE ISL59445 S1 0 0 1 1 X X S0 0 1 0 1 X X ENABLE 0 0 0 0 1 0 HIZ 0 0 0 0 X 1 OUTPUT IN0 (A, B, C) IN1 (A, B, C) IN2 (A, B, C) IN3 (A, B, C) Power Down High Z
* Broadcast Video Equipment
Ordering Information
PART NUMBER ISL59424IR ISL59424IR-T7 ISL59424IR-T13 ISL59424IRZ (Note) ISL59424IRZ-T7 (Note) PART MARKING ISL59424IR ISL59424IR ISL59424IR PACKAGE 24 Ld QFN 24 Ld QFN 24 Ld QFN TAPE & REEL 7" 13" 7" 13" 7" 13" PKG. DWG. # MDP0046 MDP0046 MDP0046 MDP0046 MDP0046 MDP0046 MDP0046 MDP0046 MDP0046
ISL59424IRZ 24 Ld QFN (Pb-free) ISL59424IRZ 24 Ld QFN (Pb-free)
ISL59424IRZ-T13 ISL59424IRZ 24 Ld QFN (Note) (Pb-free) ISL59445IR ISL59445IR-T7 ISL59445IR-T13 ISL59445IR ISL59445IR ISL59445IR 32 Ld QFN* 32 Ld QFN* 32 Ld QFN*
*32 Ld QFN Exposed Pad Size 2.48 x 3.40mm NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL59424, ISL59445 Pinouts
ISL59424 (24-PIN QFN) TOP VIEW
24 GNDA 32 GNDA 31 IN0A 23 IN0A
ISL59445 (32-PIN QFN) TOP VIEW
29 IN0B 27 IN0C
30 NIC
22 NIC
21 NIC
28 NIC
20 HIZ
IN0B 1 NIC 2 A=1 IN0C 3 GNDB 4 A=1 IN1A 5 GNDC 6 IN1B 7 NIC 8 IN1C 9 THERMAL PAD NIC 10 NIC 11 A=1
19 ENABLE 18 OUTA 17 V+ 16 OUTB 15 V14 OUTC 13 S0 LE 12
IN1A 1 NIC 2 IN1B 3 NIC 4 IN1C 5 GNDB 6 IN2A 7 NIC 8 IN2B 9 IN2C 10 GNDC 11 IN3A 12 NIC 13 IN3B 14 NIC 15 IN3C 16 A=1 THERMAL PAD A=1
26 HIZ 25 ENABLE 24 NIC 23 V+ 22 OUTA 21 V20 OUTB 19 OUTC A=1 18 S0 17 S1
THERMAL PAD INTERNALLY CONNECTED TO V-. PAD MUST BE TIED TO VLATCHED ON HIGH LE NIC = NO INTERNAL CONNECTION
THERMAL PAD INTERNALLY CONNECTED TO V-. PAD MUST BE TIED TO VNIC = NO INTERNAL CONNECTION
Functional Diagram ISL59424
S0 EN0 DECODE DL Q C DL Q C
Functional Diagram ISL59445
EN0 S0 EN1 IN0(A,B,C) IN1(A,B,C) DECODE EN2 IN2(A,B,C) IN3(A,B,C) OUT
IN0(A,B,C) IN1(A,B,C)
OUT
S1
EN1
AMPLIFIER BIAS LE HIZ HIZ ENABLE
EN3 AMPLIFIER BIAS
ENABLE A logic high on LE will latch the last S0 state. This logic state is preserved when cycling HIZ or ENABLE functions.
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ISL59424, ISL59445
Absolute Maximum Ratings (TA = 25C)
Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.5V, V+ +0.5V Supply Turn-on Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/s Digital & Analog Input Current (Note 1) . . . . . . . . . . . . . . . . . . 50mA Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7). . . .2500V Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Operating Junction Temperature . . . . . . . . . . . . . . .-40C to +125C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER GENERAL IS Enabled
V+ = +5V, V- = -5V, GND = 0V, TA = 25C, VIN = 1VP-P & RL = 500 to GND unless otherwise specified. CONDITIONS MIN TYP MAX UNIT
DESCRIPTION
Enabled Supply Current (ISL59424)
No load, VIN = 0V, Enable low, IS+ No load, VIN = 0V, Enable low, IS-
35 -40 47 -57 2 -50 -3.4 8 -35
39 -36 53 -50 3 0 -2.2 15 0
43 -32 60 -44 4
mA mA mA mA mA A
Enabled Supply Current (ISL59445)
No load, VIN = 0V, Enable low, IS+ No load, VIN = 0V, Enable low, IS-
+IS Disabled
Disabled Supply Current
Enable High, IS+ Enable High, IS-
Ib ITRI
Input Bias Current Bias current into output, HIZ mode
VIN = 0 ISL59424 - VOUT = +5V ISL59445 - VOUT = 0V VIN = 3.5V RL = 10 to GND
-1.4 22 35
A A A V mA
VOUT IOUT VOS Rout Rout RIN ACL or AV LOGIC VIH VIL IIH IIL AC GENERAL PSRR
Positive and Negative Output Swing Output Current Offset Voltage HIZ Output Resistance Enabled Output Resistance Input Resistance Voltage Gain
3.2 80
-13
3.4 130
3 1.0 0.2 10 13
mV M M
HIZ = logic high HIZ = logic low VIN = 3.5V VIN = 1.5V 0.98
0.99
1.0
V/V
Input High Voltage (Logic Inputs) Input Low Voltage (Logic Inputs) Input High Current (Logic Inputs) Input Low Current (Logic Inputs) VH = 5V VL = 0V
2 0.8 235 270 1 320 3
V V A A
Power Supply Rejection Ratio (ISL59424) Power Supply Rejection Ratio (ISL59445)
DC, PSRR V+ & V- combined DC, PSRR V+ & V- combined f = 10MHz, CL = 0.5pF, VIN = -6dBm
60 50
73 57 80 75
dB dB dB dB
ISO
Channel Isolation (ISL59424) Channel Isolation (ISL59445)
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ISL59424, ISL59445
Electrical Specifications
PARAMETER Xtalk V+ = +5V, V- = -5V, GND = 0V, TA = 25C, VIN = 1VP-P & RL = 500 to GND unless otherwise specified. CONDITIONS f = 10MHz, CL = 0.5pF, VIN = -6dBm MIN TYP 75 70 NTC-7, RL = 150, CL = 0.5pF NTC-7, RL = 150, CL = 0.5pF CL = 0.5pF CL = 0.5pF CL = 1.5pF 0.02 0.02 1000 130 200 % MHz MHz MHz MAX UNIT dB
DESCRIPTION Channel Cross Talk (ISL59424) Channel Cross Talk (ISL59445)
dG dP BW FBW
Differential Gain Error Differential Phase Error -3dB Bandwidth 0.1dB Bandwidth 0.1dB Bandwidth
SWITCHING CHARACTERISTICS SR VGLITCH ISL58424 VGLITCH ISL59445 tSW-L-H tSW-H-L tr tf tpd tS tLH Slew Rate Channel -to-Channel Switching Glitch Enable Switching Glitch HIZ Switching Glitch Channel -to-Channel Switching Glitch Enable Switching Glitch HIZ Switching Glitch Channel Switching Time Low to High Channel Switching Time High to Low Rise Time Fall Time Propagation Delay 0.1% Settling Time Latch Enable HoldTime 25% to 75%, RL = 150, Input Enabled, CL = 1.5pF, VIN = 1V VIN = 0V, CL = 0.5pF VIN = 0V, CL = 0.5pF VIN = 0V, CL = 0.5pF VIN = 0V, CL = 0.5pF VIN = 0V, CL = 0.5pF VIN = 0V, CL = 0.5pF 1.2V logic threshold to 10% movement of analog output 1.2V logic threshold to 10% movement of analog output 10% to 90% 10% to 10% 10% to 10% Step = 1V LE = 0V
1200
40 300 200 20 200 200 15 15 600 800 600 6 10
V/s mVP-P mVP-P mVP-P mVP-P mVP-P mVP-P ns ns ps ps ps ns ns
Typical Performance Curves VS = 5V, RL = 500 to GND, TA = 25C, unless otherwise specified.
10 8 6 NORMALIZED GAIN (dB) 4 2 0 -2 -4 -6 -8 -10 1 10 100 1K 1.2K FREQUENCY (MHz) CL INCLUDES 0.5pF BOARD CAPACITANCE CL=0.5pF SOURCE POWER=-12dBm CL=8.7pF CL=5.2pF NORMALIZED GAIN (dB) CL=3.8pF CL=2.7pF CL=1.5pF 5 4 3 2 1 0 -1 -2 -3 -4 -5 1 10 100 FREQUENCY (MHz) 1K 1.2K RL=150 RL=100 RL=500 SOURCE POWER=-12dBm RL=1k
FIGURE 1. GAIN vs FREQUENCY vs CL
FIGURE 2. GAIN vs FREQUENCY vs RL
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FN7456.2 September 8, 2005
ISL59424, ISL59445 Typical Performance Curves VS = 5V, RL = 500 to GND, TA = 25C, unless otherwise specified.
0.2 SOURCE 0.1 POWER =-12dBm 0 NORMALIZED GAIN (dB) -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 1 10 100 FREQUENCY (MHz) 1K 1.2K 0.1 0.1 1 10 FREQUENCY (MHz) 100 1K CL=0.5pF CL=1.5pF CL=2.0pF OUTPUT RESISTANCE () 100 SOURCE POWER =-12dBm ISL59424 10 ISL59445
(Continued)
1
FIGURE 3. 0.1dB GAIN vs FREQUENCY
FIGURE 4. ROUT vs FREQUENCY
0.8 0.6 OUTPUT VOLTAGE (V) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 TIME (5ns/DIV) RL=500 CL=1.5pF OUTPUT VOLTAGE (V)
0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 TIME (5ns/DIV) RL=500 CL=1.5pF
FIGURE 5. ISL59424 TRANSIENT RESPONSE
FIGURE 6. ISL59445 TRANSIENT RESPONSE
0 -10 -20 -30 -40 (dB) -50 -60 -70 -80 -90 -100 0.1 1 10 FREQUENCY (MHz) 100 1K OFF ISOLATION INPUT X TO OUTPUT X (dB) INPUT X TO OUTPUT Y CROSSTALK
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0.1 1 10 FREQUENCY (MHz) 100 1K OFF ISOLATION INPUT X TO OUTPUT X INPUT X TO OUTPUT Y CROSSTALK
FIGURE 7. ISL59424 CROSSTALK AND OFF ISOLATION
FIGURE 8. ISL59445 CROSSTALK AND OFF ISOLATION
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FN7456.2 September 8, 2005
ISL59424, ISL59445 Typical Performance Curves VS = 5V, RL = 500 to GND, TA = 25C, unless otherwise specified.
20 10 0 -10 PSRR (dB) PSRR (dB) -20 -30 -40 -50 -60 -70 -80 0.3 1 10 FREQUENCY (MHz) 100 1K PSRR (V-) PSRR (V+) 20 10 0 -10 -20 -30 -40 -50 -60 -70 -80 0.3 1 10 FREQUENCY (MHz) 100 1K PSRR (V-) PSRR (V+)
(Continued)
FIGURE 9. ISL59424 PSRR CHANNELS A, B, C
FIGURE 10. ISL59445 PSRR CHANNELS A, B, C
1V/DIV
1V/DIV
S0, S1 50 TERM.
VIN = 0V
S0, S1 50 TERM.
VIN = 1V
0 20mV/DIV 0.5V/DIV
0
0 VOUT A, B, C 10ns/DIV
0
VOUT A, B, C 10ns/DIV
FIGURE 11. CHANNEL TO CHANNEL SWITCHING GLITCH VIN = 0V
FIGURE 12. CHANNEL TO CHANNEL TRANSIENT RESPONSE VIN = 1V
ENABLE 50 TERM. 1V/DIV
VIN = 0V
ENABLE 50 TERM. 1V/DIV
VIN = 1V
0 100mV/DIV VOUT A, B, C 0 20ns/DIV
0
1V/DIV
0
VOUT A, B, C 20ns/DIV
FIGURE 13. ENABLE SWITCHING GLITCH VIN = 0V
FIGURE 14. ENABLE TRANSIENT RESPONSE VIN = 1V
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FN7456.2 September 8, 2005
ISL59424, ISL59445 Typical Performance Curves VS = 5V, RL = 500 to GND, TA = 25C, unless otherwise specified.
HIZ 50 TERM. 1V/DIV VIN = 0V HIZ 50 TERM. 1V/DIV
(Continued)
VIN=1V
0 200mv/DIV
0
0 VOUT A, B, C 10ns/DIV
1V/DIV
VOUT A, B, C 0 10ns/DIV
FIGURE 15. HIZ SWITCHING GLITCH VIN = 0V
FIGURE 16. HIZ TRANSIENT RESPONSE VIN = 1V
60 VOLTAGE NOISE (nV/Hz) 50 40 30 20 10 0 100
4 POWER DISSIPATION (W) 3.5 3 2.5 2 0.5 0 1K 10K 100K FREQUENCY (Hz)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD - QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 3.571W 3.378W QFN32 JA=35C/W
QFN24 JA=37C/W
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (C)
FIGURE 17. INPUT NOISE vs FREQUENCY (OUTPUT A, B, C)
FIGURE 18. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
JEDEC JESD51-3 AND SEMI G42-88 (SINGLE LAYER) TEST BOARD 0.8 0.7 POWER DISSIPATION (W) 0.6 0.5 0.4 0.3 0.2 0.1 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) QFN24 JA=140C/W 714mW 758mW QFN32 JA=125C/W
FIGURE 19. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
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FN7456.2 September 8, 2005
ISL59424, ISL59445 Pin Descriptions
ISL59445 (32-PIN QFN) 1 2, 4, 8, 13, 15, 24, 28, 30 3 5 6 7 9 10 11 12 14 16 17 18 19 20 21 22 23 25 13 14 16 15 18 17 19 6 ISL59424 (24-PIN QFN) 5 2, 8, 10, 11, 21, 22 7 9 4 PIN NAME IN1A NIC IN1B IN1C GNDB IN2A IN2B IN2C GNDC IN3A IN3B IN3C S1 S0 OUTC OUTB VOUTA V+ ENABLE Circuit 1. Circuit 1. Circuit 4. Circuit 1. Circuit 1. Circuit 1. Circuit 4. Circuit 1. Circuit 1. Circuit 1. Circuit 2. Circuit 2. Circuit 3. Circuit 3. Circuit 4. Circuit 3. Circuit 4. Circuit 2. EQUIVALENT CIRCUIT Circuit 1. DESCRIPTION Channel 1 input for output amplifier "A" Not Internally Connected; it is recommended these pins be tied to ground to minimize crosstalk. Channel 1 input for output amplifier "B" Channel 1 input for output amplifier "C" Ground pin for output amplifier "B" Channel 2 input for output amplifier "A" Channel 2 input for output amplifier "B" Channel 2 input for output amplifier "C" Ground pin for output amplifier "C" Channel 3 input for output amplifier "A" Channel 3 input for output amplifier "B" Channel 3 input for output amplifier "C" Channel selection pin MSB (binary logic code) Channel selection pin. LSB (binary logic code) Output of amplifier "C" Output of amplifier "B" Negative power supply Output of amplifier "A" Positive power supply Device enable (active low). Internal pull-down resistor ensures the device will be active with no connection to this pin. A logic High on this pin puts device into powerdown mode. In power-down mode only logic circuitry is active. All logic states are preserved post power-down. This state is not recommended for logic control where more than one MUX-amp share the same video output line. Device latch enable on the ISL59424. A logic high on LE will latch the last (S0, S1) logic state. HIZ and ENABLE functions are not latched with the LE pin. Output disable (active high). Internal pull-down resistor ensures the device will be active with no connection to this pin. A logic high, puts the outputs in a high impedance state. Use this state to control logic when more than one MUX-amp share the same video output line. Channel 0 for output amplifier "C" Channel 0 for output amplifier "B" Channel 0 for output amplifier "A" Ground pin for output amplifier "A"
V+ LOGIC PIN VCIRCUIT 1 21K 33K + 1.2V GND. VCIRCUIT 2 CIRCUIT 3 V+ OUT V-
12 26 20
LE HIZ
Circuit 2. Circuit 2.
27 29 31 32
3 1 23 24
IN0C IN0B IN0A GNDA
V+
Circuit 1. Circuit 1. Circuit 1. Circuit 4.
IN
THERMAL HEAT SINK PAD V+ GNDA GNDB GNDC V. CIRCUIT 4
CAPACITIVELY COUPLED ESD CLAMP
~1M
VSUBSTRATE
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FN7456.2 September 8, 2005
ISL59424, ISL59445 AC Test Circuits
ISL59424 & ISL59445 ISL59424 & ISL59445 VIN 50 or 75 CL 1.5pF RL 500 VIN 50 or 75 CL 1.5pF RS 475 or 462.5 50 or 75 TEST EQUIPMENT 50 or 75
FIGURE 20A. TEST CIRCUIT WITH OPTIMAL OUTPUT LOAD
FIGURE 20B. TEST CIRCUIT FOR MEASURING WITH 50 OR 75 INPUT TERMINATED EQUIPMENT
TEST EQUIPMENT 50 or 75
ISL59424 & ISL59445 VIN 50 or 75 RS 50 or 75 CL 1.5pF
FIGURE 20C. BACKLOADED TEST CIRCUIT FOR VIDEO CABLE APPLICATION. BANDWIDTH AND LINEARITY FOR RL LESS THAN 500 WILL BE DEGRADED. FIGURE 20. TEST CIRCUITS
Figure 20A illustrates the optimum output load for testing AC performance. Figure 20B illustrates the optimum output load when connecting to 50 input terminated equipment.
Power-Up Considerations
The ESD protection circuits use internal diodes from all pins the V+ and V- supplies. In addition, a dV/dT- triggered clamp is connected between the V+ and V- pins, as shown in the Equivalent Circuits 1 through 4 section of the Pin Description table. The dV/dT triggered clamp imposes a maximum supply turn-on slew rate of 1V/s. Damaging currents can flow for power supply rates-of-rise in excess of 1V/s, such as during hot plugging. Under these conditions, additional methods should be employed to ensure the rate of rise is not exceeded. Consideration must be given to the order in which power is applied to the V+ and V- pins, as well as analog and logic input pins. Schottky diodes (Motorola MBR0550T or equivalent) connected from V+ to ground and V- to ground (Figure 21) will shunt damaging currents away from the internal V+ and V- ESD diodes in the event that the V+ supply is applied to the device before the V- supply. If positive voltages are applied to the logic or analog video input pins before V+ is applied, current will flow through the internal ESD diodes to the V+ pin. The presence of large decoupling capacitors and the loading effect of other circuits connected to V+, can result in damaging currents through the ESD diodes and other active circuits within the device. Therefore, adequate current limiting on the digital and analog inputs is needed to prevent damage during the time the voltages on these inputs are more positive than V+.
Application Information
General
The ISL59424 and ISL59445 are triple 2:1 and 4:1 muxes that are ideal for the matrix element of high performance switchers and routers. The ISL59424 and ISL59445 are optimized to drive a 1.5pF in parallel with a 500 load. The capacitance can be split between the PCB capacitance an and external load capacitance. Their low input capacitance and high input resistance provide excellent 50 or 75 terminations.
Ground Connections
For the best isolation and crosstalk rejection, all GND pins and NIC pins must connect to the GND plane.
Control Signals
S0, S1, ENABLE, LE, HIZ - These pins are binary coded, TTL/CMOS compatible control inputs. The S0, S1 pins select which one of the inputs connect to the output. All three amplifiers are switched simultaneously from their respective inputs. The ENABLE, LE, HIZ pins are used to disable the part to save power, latch in the last logic state and three-state the output amplifiers, respectively. For control signal rise and fall times less than 10ns the use of termination resistors close to the part should be considered to minimize transients coupled to the output.
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ISL59424, ISL59445
V+ SUPPLY LOGIC POWER GND SIGNAL DE-COUPLING CAPS V- SUPPLY
SCHOTTKY PROTECTION S0 GND IN0 IN1
V+
V+ LOGIC CONTROL
EXTERNAL CIRCUITS
VV+
V+ V+ OUT VV-
V-
V-
FIGURE 21. SCHOTTKY PROTECTION CIRCUIT
HIZ State
An internal pull-down resistor connected to the HIZ pin ensures the device will be active with no connection to the HIZ pin. The HIZ state is established within approximately 15ns (Figure 16) by placing a logic high (>2V) on the HIZ pin. If the HIZ state is selected, the output is a high impedance 1.4M with approximately 1.5pF in parallel with a 10A bias current from the output. Use this state to control the logic when more than one mux shares a common output. In the HIZ state the output is three-stated, and maintains its high Z even in the presence of high slew rates. The supply current during this state is basically the same as the active state.
RGB video and disconnects the sync signal for the component signal.
PC Board Layout
The frequency response of this circuit depends greatly on the care taken in designing the PC board. The following are recommendations to achieve optimum high frequency performance from your PC board. * The use of low inductance components such as chip resistors and chip capacitors is strongly recommended. * Minimize signal trace lengths. Trace inductance and capacitance can easily limit circuit performance. Avoid sharp corners, use rounded corners when possible. Vias in the signal lines add inductance at high frequency and should be avoided. PCB traces greater than 1" begin to exhibit transmission line characteristics with signal rise/fall times of 1ns or less. High frequency performance may be degraded for traces greater than one inch, unless strip line are used. * Match channel-channel analog I/O trace lengths and layout symmetry. This will minimize propagation delay mismatches. * Maximize use of AC de-coupled PCB layers. All signal I/O lines should be routed over continuous ground planes (i.e. no split planes or PCB gaps under these lines). Avoid vias in the signal I/O lines. * Use proper value and location of termination resistors. Termination resistors should be as close to the device as possible. * When testing use good quality connectors and cables, matching cable types and keeping cable lengths to a minimum. * Minimum of 2 power supply de-coupling capacitors are recommended (1000pF, 0.01F) as close to the devices as possible - Avoid vias between the cap and the device because vias add unwanted inductance. Larger caps can be farther away. When vias are required in a layout, they should be routed as far away from the device as possible. * The NIC pins are placed on both sides of the input pins. These pins are not internally connected to the die. It is recommended these pins be tied to ground to minimize crosstalk.
ENABLE and Power Down States
The enable pin is active low. An internal pull-down resistor ensures the device will be active with no connection to the ENABLE pin. The Power Down state is established within approximately 100ns (Figure 14), if a logic high (>2V) is placed on the ENABLE pin. In the Power Down state, the output has no leakage but has a large variable capacitance (on the order of 15pF), and is capable of being back-driven. Under this condition, large incoming slew rates can cause fault currents of tens of mA. Do not use this state as a logic control for applications driving more than one mux on a common output.
LE State
The ISL59424 is equipped with a Latch Enable pin. A logic high (>2V) on the LE pin latches the last logic state. This logic state is preserved when cycling HIZ or ENABLE functions.
Limiting the Output Current
No output short circuit current limit exists on these parts. All applications need to limit the output current to less than 50mA. Adequate thermal heat sinking of the parts is also required.
Application Example
Figure 21 illustrates the use of the ISL59445, two ISL84517 SPST switches and one NC7ST00P5X NAND gate to mux 3 different component video signals and one RGB video signal. The SPDT switches provide the sync signal for the 10
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ISL59424, ISL59445
The QFN Package Requires Additional PCB Layout Rules for the Thermal Pad
The thermal pad is electrically connected to V- supply through the high resistance IC substrate. Its primary function is to provide heat sinking for the IC. However, because of the connection to the V- supply through the substrate, the thermal pad must be tied to the V- supply to prevent unwanted current flow to the thermal pad. Do not tie this pin to GND. Connecting this pin to GND could result in large back biased currents flowing between GND and V-. The ISL59445 uses the package with pad dimensions of D2 = 2.48mm and E2 = 3.4mm. Maximum AC performance is achieved if the thermal pad is attached to a dedicated de-coupled layer in a multi-layered PC board. In cases where a dedicated layer is not possible, AC performance may be reduced at upper frequencies. The thermal pad requirements are proportional to power dissipation and ambient temperature. A dedicated layer eliminates the need for individual thermal pad area. When a dedicated layer is not possible a 1" x 1" pad area is sufficient for the ISL59445 that is dissipating 0.5W in +50C ambient. Pad area requirements should be evaluated on a case by case basis.
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FN7456.2 September 8, 2005
5V OPTIONAL SCHOTTKY PROTECTION
0.1F
0.1F
-5V
Y1 Y2 Y3 R
31 1 7 12
INOA IN1A IN2A IN3A
ISL59445IL
V+ VOUTA OUTB
23 21 22 20 19 32 6 11 2 4 8 13 15
1nF
1nF
Pb1 Pb2 Pb3 G
29 3 9 14
INOB IN1B IN2B IN3B
OUTC GNDA GNDB GNDC NIC NIC NIC NIC NIC NIC NIC NIC HIZ
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FN7456.2 September 8, 2005
R16 500 R17 500
R18 500
Pr1 Pr2 Pr3 B
27 5 10 16
INOC IN1C IN2C IN3C
ISL59424, ISL59445
24 28 30 26
R1 75 R2 75
R3 75 R4 75
R5 75 R6 75
R7 75 R8 75
R9 75 R10 75
R11 75 R12 75 QFN
ENABLE 25 S0 18 S1 17
5V
0.1F
0.1F
-5V
H SYNC
1 -5V
ISL84517IH-T COM SOT-23 IN 4 V+ V-
5 3
1nF
1nF
5V
0.1F
0.1F
NC 2 5V NC7ST00P5X 5V 5 INPUT 1 4 OUT 3 GND INPUT 2 SC70 LOGIC INPUTS 1nF 0.1F
ISL84517IH-T V SYNC 1 COM SOT-23 IN 4 V+ V-
5 3
1nF
1nF
NC 2
FIGURE 22. APPLICATION SHOWING THREE YPBPR CHANNELS AND ONE RGB+HV CHANNEL
ISL59424, ISL59445 QFN Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 13
FN7456.2 September 8, 2005

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